View MAX3674ECM_4132489.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2483; Rev 0; 12/07
High-Performance, Dual-Output, Network Clock Synthesizer
General Description
The MAX3674 is a high-performance network clock synthesizer IC for networking, computing, and telecom applications. It integrates a crystal oscillator, a lownoise phase-locked loop (PLL), programmable dividers, and high-frequency LVPECL output buffers. The PLL generates a high-frequency clock based on a low-frequency reference clock provided by the on-chip crystal oscillator or an external LVCMOS clock. The MAX3674 has excellent period jitter, cycle-to-cycle jitter, and supply noise rejection performance. With output frequencies programmable from 21.25MHz to 1360MHz and support of two differential PECL output signals, the device provides a versatile solution for the most demanding clock applications. Programming is accomplished through a 2-wire I2C bus or parallel interface that can change the output frequency on demand for frequency margining. Both LVPECL outputs have synchronous stop functionality, and the PLL has a LOCK indicator output. The MAX3674 operates from a +3.3V supply and typically consumes 396mW. The device is packaged in a 48-pin LQFP, and the operating temperature range is from -40C to +85C.
Features
21.25MHz to 1360MHz Programmable PLL Synthesized Output Clocks Two Differential LVPECL-Compatible Outputs Cycle-to-Cycle Jitter 1.6ps RMS and Period Jitter 0.9ps RMS at 500MHz On-Chip Crystal Oscillator or Selectable LVCMOS-Compatible Reference Clock Input Excellent Power-Supply Noise Rejection Parallel or 2-Wire I2C Programming Interface Lock Indicator Output +3.3V Power Supply Power Consumption: 396mW at 3.3V 48-Pin LQFP Pb-Free Package -40C to +85C Temperature Range
MAX3674
Ordering Information
PART MAX3674ECM+ TEMP RANGE -40C to +85C PIN-PACKAGE 48 LQFP
Applications
Ethernet Network ASIC Clock Generation Storage Area Network ASIC Clocking Optical Network ASIC Clocking Programmable Clock Source for Server, Computing, or Communication Systems Frequency Margining
+Denotes a lead-free package.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V +3.3V REF_SEL REF_CLK XTAL1 16MHz XTAL2 SERIAL I2C INTERFACE PARALLEL INTERFACE PLL DIVIDER CONTROLS SDA SCL M[9:0] NA[2:0] NB P PLOAD MR +3.3V VCC +3.3V VCC_PLL QA QA QB QB NETWORK ASIC LVPECL OUTPUTS Z = 50
130
MAX3674
CLK_STOPA CLK_STOPB BYPASS +3.3V
82
GND LOCK
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VCC and VCC_PLL)...........-0.3V to +3.9V DC Input Voltage Range (BYPASS, REF_SEL, REF_CLK, CLK_STOPx, XTAL1, XTAL2, M[9:0], TEST_EN, NB, NA[2:0], PLOAD, MR, SDA, SCL, ADR[1:0], P) to GND ......-0.3V to (VCC + 0.3V) DC Output Voltage Range (LOCK, SDA, Qx, Qx) ....................................................-0.3V to (VCC + 0.3V) DC Input Current...............................................................20mA DC Output Current ............................................................50mA Continuous Power Dissipation (TA = +70C) 48-Pin LQFP (derate 21.7mW/C above 70C) ..........1739mW Operating Ambient Temperature Range (TA)......-40C to +85C Operating Junction Temperature (TJ)..............................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC_PLL = +3.3V 5%, TA = -40C to +85C, BYPASS = high, TEST_EN = low. Typical values are at VCC = VCC_PLL = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX VCC + 0.3 +0.8 200 4.0 VCC + 0.3 +0.8 10 0.4 2.4 0.4 VCC 1.25 VCC 1.95 3.135 (Note 4) Includes PECL output currents (Note 3) PECL outputs open 3.035 3.3 3.3 120 81 10 VCC 0.74 VCC 1.45 3.465 3.465 136 UNITS LVCMOS INPUTS (BYPASS, REF_SEL, REF_CLK, CLK_STOPx, M[9:0], TEST_EN, NB, NA[2:0], PLOAD, MR, ADR[1:0], P) Input High Voltage Input Low Voltage Input Current Input Capacitance I2C INPUTS (SDA, SCL) Input High Voltage Input Low Voltage Input Current I2C OPEN-DRAIN OUTPUT (SDA) Output Low Voltage LVCMOS/TTL OUTPUT (LOCK) Output High Voltage Output Low Voltage VOH VOL I OH = -4mA I OL = +4mA V V VOL I OL = +4mA V VIH VIL I IH, I IL VIN = VCC or GND 2.0 -0.3 V V A VIH VIL I IH, I IL CIN VIN = VCC or GND (Note 2) 2.0 -0.3 V V A pF
LVPECL DIFFERENTIAL CLOCK OUTPUTS (Qx, Qx) Output High Voltage Output Low Voltage POWER SUPPLY Supply Voltage PLL Supply Voltage Supply Current PLL Supply Current VCC VCC_PLL ICC ICC_PLL V V mA mA VOH VOL (Note 3) (Note 3) V V
2
_______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC_PLL = +3.3V 5%, TA = -40C to +85C, NB = 1 (low), P = 4 (high), BYPASS = high, TEST_EN = low. Typical values are at VCC = VCC_PLL = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Input Frequency Input Rise/Fall Time Input Duty Cycle CRYSTAL OSCILLATOR (XTAL1, XTAL2) Crystal Input Frequency VCO Frequency f XTAL f VCO (Note 5) NA = 2 NA = 4 Output Frequency (Note 6) f OUT NA = 8 NA = 16 NA = 32 NA = 64 f QA = f QB Output Clock Duty Cycle DC f QA = f QB f QA = f QB 500MHz 680MHz 1360MHz f QB), f QA 500MHz 45 0.49 1360MHz 0.32 2 2 tQx tQx 3.7 6.4 8.5 13 35 2.5 3.7 4.9 7 18 -38 psP-P dBc psRMS (1 ) psP-P psRMS (1 ) 15 1360 680 340 170 85.0 42.5 21.25 46.0 44.8 42.0 50 50 50 10 340 1.0 1.0 16 20 2720 1360 680 340 170 85.0 42.50 54.0 55.2 56.8 38 ps ps VP-P % MHz MHz MHz CLOCK OUTPUT PERFORMANCE (Qx, Qx) (Note 3) SYMBOL fREF_CLK 20% to 80% 30 CONDITIONS MIN 15 TYP 16 5 70 MAX 20 UNITS MHz ns %
MAX3674
EXTERNAL REFERENCE CLOCK INPUT (REF_CLK)
Output-to-Output Skew Output Rise/Fall Time Output Peak-to-Peak Voltage (Single-Ended) (Note 7) Output Enable Time Output Disable Time t EN tDIS tR, tF
NB = 1 (f QA = f QB) (Note 7) NB = 2 (f QA = 2 20% to 80% f OUT 1000MHz 1000MHz < f OUT
Figures 3 and 4, t Qx = output period Figures 3 and 4, t Qx = output period NA = 2 NA = 4
Cycle-to-Cycle Jitter (Notes 7, 8)
JCC
NA = 8, 16, 32, 64 NA = 4, NB = 1 NA = 4, NB = 2 (Note 9) NA = 2 NA = 4
Period Jitter (Notes 7, 8)
J PER
NA = 8, 16, 32, 64 NA = 4, NB = 1 NA = 4, NB = 2 (Note 9)
Relative Sideband Spur Power Due to Power-Supply Noise
(Note 10)
_______________________________________________________________________________________
3
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC_PLL = +3.3V 5%, TA = -40C to +85C, NB = 1 (low), P = 4 (high), BYPASS = high, TEST_EN = low. Typical values are at VCC = VCC_PLL = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER PLL Closed-Loop Bandwidth (Note 11) PLL Lock Time PLL Acquisition Time When Incrementing or Decrementing M CONTROL TIMING (PLOAD, MR) PLOAD Pulse Width MR Pulse Width SERIAL INTERFACE I2C (SDA, SCL) I2C Clock Frequency SDA Output Fall Time f SCL tF (Note 14) 400 300 kHz ns 50 50 ns ns tLOCK SYMBOL P=2 P=4 (Note 12) (Note 13) CONDITIONS MIN TYP 150 to 450 75 to 225 3 50 6 MAX UNITS kHz ms s
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14:
Specifications +25C guaranteed by production test, < +25C guaranteed by design and characterization. Inputs have pullup and pulldown resistors affecting the input current. Outputs terminated 50 to VTT = VCC - 2V. See the AC Electrical Characteristics section for Peak-to-Peak Voltage. PLL supply voltage must also satisfy VCC_PLL VCC + 0.3V. The reference clock input frequency fXTAL (and fREF_CLK) and the PLL divider M and P must match the VCO frequency range: fVCO = fXTAL x M / P for stable PLL operation. The output frequency for QA and QB if NB = 1 (low) and fREF = 16MHz. With NB = 2 (high) the QB output frequency is half the QA output frequency. Guaranteed by design and characterization over full temperature range (-40C to +85C). Selecting crystal oscillator as reference with fXTAL= 16MHz. When NB = 2 (high), the QA output has a bimodal jitter distribution. Sample size = 20,000 cycles. Measured as spur in frequency domain with 50mVP-P sinusoidal noise (10kHz to 10MHz) on the supply. See the Typical Operating Characteristics. -3dB point of PLL transfer characteristics. Time period from master reset release (MR rising edge) to when PLL indicates lock (LOCK rising edge). Valid for both crystal (after crystal oscillator stabilized) and reference clock inputs. Time period after incrementing or decrementing (M < 5) within valid M range to when PLL indicates lock (LOCK rising edge). An appropriate bus pullup resistance must be selected depending on board capacitance.
4
_______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
Typical Operating Characteristics
(VCC = VCC_PLL = +3.3V, TA = +25C, fQA = fQB = 500MHz (P = 4, NA = 4, NB = 1, M = 500), REF_SEL= high (crystal oscillator), fXTAL = 16MHz, unless otherwise noted.)
CYCLE-TO-CYCLE JITTER vs. VCO FREQUENCY
MAX3674 toc01
MAX3674
PERIOD JITTER vs. VCO FREQUENCY
MAX3674 toc02
PHASE NOISE
-60 -70 PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 P=2
MAX3674 toc03
5 CYCLE-TO-CYCLE JITTER (psRMS) NA = 16, 32, 64 4 NA = 8 3 NA = 4 2
5
-50 P=4
4 PERIOD JITTER (psRMS) NA = 16, 32, 64 3 NA = 8 2 NA = 4
1 NA = 2
1 NA = 2
-140 -150 2448 2720 100 1k 10k 100k 1M 10M 100M
0 1360 1632 1904 2176 2448 2720 VCO FREQUENCY (MHz)
0 1360 1632 1904 2176 VCO FREQUENCY (MHz)
OFFSET FREQUENCY (Hz)
OUTPUT PEAK-TO PEAK VOLTAGE vs. OUTPUT FREQUENCY
MAX3674 toc04
OUTPUT RISE/FALL TIME vs. OUTPUT FREQUENCY
MAX3674 toc05
OUTPUT-TO-OUTPUT SKEW vs. OUTPUT FREQUENCY
MAX3674 toc06
900 850 SINGLE-ENDED VOLTAGE (mVP-P) 800 750 700 650 600 550 500 450 400 0 200 400 600 800
350
300 OUTPUT-TO-OUTPUT SKEW (ps) 250 200 NB = 2, (fQA = 2 x fQB) 150 100 NB = 1, (fQA = fQB) 50 0
OUTPUT RISE/FALL TIME (ps)
300
250
200
150
100 1000 1200 1400 0 200 400 600 800 1000 1200 1400 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz)
0
200
400
600
800
1000 1200 1400
QA OUTPUT FREQUENCY (MHz)
Qx CLOCK OUTPUT (SINGLE-ENDED)
MAX3674 toc07
TOTAL SUPPLY CURRENT vs. TEMPERATURE
INCLUDES PECL OUTPUT CURRENTS TOTAL SUPPLY CURRENT (mA) 140 130 120 110 100 90
MAX3674 toc08
PLL SUPPLY CURRENT vs. VCO FREQUENCY
12 11 10 9 8 7 6 5 4 3 2 1 0 1360 1632 1904 2176 2448 2720 VCO FREQUENCY (MHz)
MAX3674 toc09
150
500ps/div
-50
-25
0
25
50
75
100
TEMPERATURE (C)
_______________________________________________________________________________________
PLL SUPPLY CURRENT (mA)
100mV/div
5
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
Typical Operating Characteristics (continued)
(VCC = VCC_PLL = +3.3V, TA = +25C, fQA = fQB = 500MHz (P = 4, NA = 4, NB = 1, M = 500), REF_SEL= high (crystal oscillator), fXTAL = 16MHz, unless otherwise noted.)
RELATIVE SIDEBAND SPUR POWER DUE TO POWER-SUPPLY NOISE
MAX3674 toc10
PLL LOCK TIME vs. VCO FREQUENCY (MR DEASSERT TO LOCK ASSERT)
MAX3674 toc11
PLL ACQUISITION TIME WHEN INCREMENTING/DECREMENTING M
450 400 ACQUISITION TIME (s) 350 300 250 200 150 100 50 P=4 P=2
MAX3674 toc12
-20 RELATIVE SIDEBAND SPUR POWER (dBc) -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 10k 100k 1M SINUSOIDAL SUPPLY NOISE = 50mVP-P
6
500
5 PLL LOCK TIME (ms) P=4 4
3 P=2
2
1 10M 1360 1632 1904 2176 2448 2720 SUPPLY NOISE FREQUENCY (Hz) VCO FREQUENCY (MHz)
0 0 5 10 15 20 25 30 35 40 45 50 M (DECIMAL VALUE)
JITTER vs. SUPPLY NOISE FREQUENCY
MAX3674 toc13
CYCLE-TO-CYCLE JITTER (PEAK-TO-PEAK) vs. VCO FREQUENCY
MAX3674 toc14
PERIOD JITTER (PEAK-TO-PEAK) vs. VCO FREQUENCY
90 80 PERIOD JITTER (psP-P) 70 60 50 40 30 20 10 0 NB = 1 NB = 2 SAMPLE = 20,000 CYCLES QA OUTPUT, NA = 4
MAX3674 toc15
5 SINUSOIDAL SUPPLY NOISE = 50mVP-P 4 JITTER (psRMS) CYCLE-TO-CYCLE JITTER 3 PERIOD JITTER 2
100 90 CYCLE-TO-CYCLE JITTER (psP-P) 80 70 60 50 40 30 20 10 NB = 1 NB = 2 SAMPLE = 20,000 CYCLES QA OUTPUT, NA = 4
100
1
0 10k 100k 1M 10M SUPPLY NOISE FREQUENCY (Hz)
0 1360 1632 1904 2176 2448 2720 VCO FREQUENCY (MHz)
1360
1632
1904
2176
2448
2720
VCO FREQUENCY (MHz)
6
_______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
Pin Description
PIN 1, 4, 13, 30, 34, 36, 42 2 3, 8, 19, 27, 31, 37 5 6 7 9, 10 11, 12 14-18, 20-24 25 26 28 29 32 33 35 38, 39, 40 41 43 44 45 46, 47 48 NAME VCC BYPASS GND I/O Supply Input Supply TYPE VCC LVCMOS Ground Positive Power Supply Selects the Static Circuit Bypass Mode Ground Positive Power Supply for the PLL (Analog Power Supply). It is recommended to use an external passive filter for the supply pin VCC_PLL. See Figure 5. Selects Reference Clock Input PLL External Reference Clock Input Output Qx Disable in Logic-Low State Crystal Oscillator Interface PLL Feedback-Divider Configuration Factory Test Mode Enable. This pin must be connected to GND in all applications of the device. PLL Lock Indicator Channel B Differential Clock Output Channel A Differential Clock Output PLL Postdivider Configuration for Output QB PLL Postdivider Configuration for Output QA and QB Selects the Programming Interface for Parallel or I2C Device Master Reset I2C Data I2C Clock Selectable Two Bits of the I2C Slave Address PLL Predivider Configuration FUNCTION
MAX3674
VCC_PLL REF_SEL REF_CLK CLK_STOPA, CLK_STOPB XTAL1, XTAL2 M[9:0] TEST_EN LOCK QB QB QA QA NB NA[2:0] PLOAD MR SDA SCL ADR[1:0] P
Supply Input Input Input Input Input Input Output Output Output Input Input Input Input Input/ Output Input Input Input
VCC LVCMOS LVCMOS LVCMOS Analog LVCMOS LVCMOS LVCMOS LVPECL LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS/ Open Drain LVCMOS LVCMOS LVCMOS
_______________________________________________________________________________________
7
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
Function Table
PIN INPUT PINS REF_SEL P M[9:0] NA[2:0] NB 1 1 01 1111 0100 b (Note 2) 010 0 Selects REF_CLK input as PLL reference clock. Selects XTAL interface as PLL reference clock. DEFAULT (Note 1) FUNCTION WHEN SET LOW 0 FUNCTION WHEN SET HIGH 1
PLL predivider parallel programming interface. See Table 4. PLL feedback-divider (10-bit) parallel programming interface. See Table 5. PLL postdivider parallel programming interface. See Table 6. PLL postdivider parallel programming interface. See Table 7. Selects the parallel programming interface. The internal PLL divider settings (M, NA, NB, and P) are equal to the setting of the hardware pins. Leaving the M, NA, NB, and P pins open (floating) results in a default PLL configuration with f OUT = 250MHz. PLL settings can be read through the I2C interface. Address bit = 0
PLOAD
0
Selects the serial (I2C) programming interface. The internal PLL divider settings (M, NA, NB, and P) are set and read through the serial interface.
ADR[1:0] SDA, SCL
00 --
Address bit = 1
See the Programming Through Serial I2C Interface section. PLL function bypassed. f QA = fREF / NA and f QB = fREF / (NA NB) LOCK = test output Normal operation mode. Factory test mode disabled. Output Qx is synchronously disabled in logic-low state. PLL function enabled. f QA = (fREF / P) M / NA and f QB = (fREF / P) M / (NA NB) Factory test mode enabled. Output Qx is synchronously enabled.
BYPASS
1
TEST_EN CLK_STOPx
0 1
MR
--
The device is reset. The output frequency is zero and the outputs are asynchronously forced to a logic-low state. After releasing reset (upon the The PLL attempts to lock to the reference rising edge of MR and independent on the signal. The tLOCK specification applies. state of PLOAD), the MAX3674 reads the parallel interface (M, NA, NB, and P) to acquire a valid startup frequency configuration. PLL is not locked. PLL is frequency locked.
OUTPUT PIN LOCK --
Note 1: Default states are set by internal input 75k pullup or pulldown resistors. Note 2: If fREF = 16MHz, the default configuration results in a 250MHz output frequency.
8
_______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
Detailed Description
The MAX3674 is a high-performance wide-frequency range clock synthesizer. It integrates a crystal oscillator, PLL, programmable dividers, configuration registers, two differential PECL outputs buffers (QA, QB), and an LVCMOS lock indicator output (Figure 1). Using a lowfrequency clock as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance. The programmable dividers make it possible to generate a wide range of output frequencies (21.25MHz to 1360MHz) and perform frequency margining using the increment and decrement functions. divided-down VCO output (fVCO / M) and generates a control signal that keeps the VCO locked to the reference clock. After scaling the VCO output with postdividers (NA,B), the high-frequency clock is sent to the PECL output buffers. To minimize noise-induced jitter, the PLL supply (VCC_PLL) is isolated from the supply for the core logic and output buffers.
MAX3674
Configuration Registers and Dividers
Output frequency depends on the reference clock frequency fREF, the predivider P, the feedback divider M, and the postdividers NA,B. Dividers are programmable through configuration logic that uses either a serial or parallel interface as selected by the PLOAD input. The parallel interface uses the values at the P, M[9:0], NA[2:0], and NB parallel inputs to configure the internal dividers. The serial interface is I2C compatible and provides read and write access to configuration registers.
Reference Clock
An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external quartz crystal connected between XTAL1 and XTAL2 (Table 12). Alternatively, an LVCMOS-compatible clock source can be connected to the REF_CLK input to serve as the reference clock.
LVPECL Outputs
The high-frequency outputs, QA and QB, use differential PECL buffers designed to drive a pair of transmission lines terminated 50 to VTT = VCC - 2.0V. Both differential outputs can be enabled/disabled independently using the CLK_STOPx inputs. The CLK_STOPx inputs are synchronized to the output clock signal to eliminate the possibility of producing runt pulses. Using the postdivider NB, the secondary output QB can be configured to run at 1x or 1/2x the frequency of the primary output QA.
Phase-Locked Loop (PLL)
The reference clock passes through a predivider (P) before entering the PLL. The PLL contains a phase-frequency detector (PFD), lowpass filter, and voltage-controlled oscillator (VCO) with a 1360MHz to 2720MHz operating range. The VCO output is connected to the PFD input through a feedback divider (M). The PFD compares the divided reference clock (fREF / P) to the
REF_CLK XTAL1 XTAL2 REF_SEL SDA SCL ADR[1:0] P PLOAD M[9:0] NA[2:0] NB CLK_STOPx BYPASS MR XTAL fREF
/P (2, 4)
PLL 1360MHz TO 2720MHz /M
fVCO
/ NA (2, 4, 8, 16, 32, 64)
fQA
QA
/ NB (1, 2)
fQB
QB
I2C/PARALLEL PLL CONFIGURATION REGISTERS LOCK
MAX3674
Figure 1. Functional Diagram
_______________________________________________________________________________________ 9
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
Lock Indicator
The PFD within the PLL generates the lock indicator and operates by comparing the divided down VCO output (fVCO / M) to a divided down reference clock (fREF / P). The LOCK output pin indicates that the PLL is locked (LOCK = 1) when the VCO has obtained phase and frequency lock with the reference clock. See the LOCK Detect section in the Applications Information section for further details.
Internal Register Definitions
The MAX3674 has four 8-bit-wide internal registers for accessing through the I 2 C interface. The registers include two configuration registers (PLL_L and PLL_H), a command register (CMD), and an ID register (ID). Tables 1 and 2 show the register map, definitions, and default values.
Table 1. Register Map
ADDRESS 0x00h 0x01h 0xF0h 0x08h NAME PLL_L PLL_H CMD ID CONTENT Least significant 8 bits of PLL feedback divider M, M[7:0] Most significant 2 bits of M, M[9:8] and NA[2:0], NB, P, LOCK Command register Unique bit pattern for identification (8'b01010100) ACCESS R/W R/W W R
Table 2. Register Definition and Default Values
REGISTER PLL_L PLL_H BIT 7 (MSB) M7 1 M9 0 x x x x ID 0 BIT 6 M6 1 M8 1 x x x x 1 BIT 5 M5 1 NA2 0 x x x x 0 BIT 4 M4 1 NA1 1 x x x x 1 BIT 3 M3 0 NA0 0 0 0 0 1 0 BIT 2 M2 1 NB 0 0 0 1 0 1 BIT 1 M1 0 P 1 0 1 0 0 0 BIT 0 (LSB) M0 0 LOCK x 1 0 0 0 0
Command INC (0x01), increase internal PLL frequency M := M + 1 Command DEC (0x02), decrease internal PLL frequency M := M - 1 CMD Command LOAD (0x04), update PLL divider configuration, PLL divider M, NA, NB, P := PLL_L, PLL_H Command GET (0x08), update the configuration registers, PLL_L, PLL_H := PLL divider M, NA, NB, P MAX3674 unique device ID
10
______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
I2C Characteristics The MAX3674 acts as a slave device on the I2C bus supporting fast-mode data transfer (up to 400kbps). Its clock pin, SCL, is an input only. It does not support clock stretching. Table 3 shows the I2C slave address.
frequency of the synthesizer on the fly using the increment and decrement functions for frequency margining applications. An LVCMOS-compatible input (PLOAD) is used to select the parallel interface or serial interface, as described in the Function Table.
MAX3674
Table 3. I2C Slave Address
BIT VALUE 7 (MSB) 1 6 0 5 1 4 1 3 0 2 1 0 (LSB)
ADR1 ADR0 R/W
Output Frequency Configuration The MAX3674 output frequency (fOUT) is a function of the reference frequency (fREF) and the programmable dividers (P, M, and NA,B) and is expressed as:
f M f OUT = REF x P N A,B The numbers P, M, NA, and NB are divider ratios requiring configuration through parallel programming or I2C serial interfaces using registers PLL_L and PLL_H. P is the predivider to the input of the phase-locked loop (PLL) and has a valid division ratio of 2 or 4 (Table 4). P can be set by the parallel interface pin P or through the serial I2C interface. M is determined by the inputs at the 10-pin M[9:0] through parallel interface or by programming through the serial I 2C interface (Table 5). NA determines the postdivider for differential output QA and QB, and has a valid division value of 2, 4, 8, 16, 32, or 64 based on the 3-pin inputs NA[2:0] (Table 6). NA can also be set through the serial I2C interface. NB is the postdivider for output QB and has a valid value of 1 or 2 (Table 7). NB can be set by the parallel interface pin NB or through the serial I2C interface.
The slave address is composed of a 5-bit fixed address and 2-bit variable address that is set by the input pins ADR[1:0]. The variable address pins are used to avoid address conflicts of multiple MAX3674 devices on the same I2C bus. The host controller uses bit 0 (LSB) of the MAX3674 slave address to select either read or write mode. "0" indicates I2C "write" to the MAX3674 registers; "1" indicates I2C "read" from the MAX3674 registers.
Applications Information
Programming the MAX3674
The MAX3674 PLL configurations can be controlled either through the parallel interface or the serial I2C interface. The parallel interface allows the user to directly configure the PLL dividers through hardwired pins without the overhead of a serial interface. At device startup, the device always obtains an initial PLL frequency configuration through the parallel interface. The PLL configuration can be read through I2C in parallel interface mode. The serial interface is I2C compatible. It allows reading and writing device settings through built-in registers. It also allows a host controller to program the output
Table 4. Pre-PLL Divider P
P 0 1 VALUE fREF / 2 fREF / 4 DEFAULT VALUE -- 1
Table 5. PLL Feedback Divider M
M[9:0] 136 137 ... 500 ... 512 ... 724 725 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 M9 0 0 M8 0 0 M7 1 1 M6 0 0 M5 0 0 M4 0 0 M3 1 1 M2 0 0 M1 0 0 M0 0 1 DEFAULT VALUE -- -- -- 01 1111 0100 -- -- -- -- --
______________________________________________________________________________________
11
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
Table 6. Post-PLL Divider NA
NA2 0 1 0 1 0 1 NA1 0 0 1 1 0 0 NA0 0 0 0 0 1 1 fOUT (QA) f VCO / 2 f VCO / 4 f VCO / 8 f VCO / 16 f VCO / 32 f VCO / 64 DEFAULT VALUE -- -- 010 -- -- --
Table 8 shows an example of the output frequency resolution at different output frequencies, assuming a 16MHz reference clock is used.
Table 8. Frequency Ranges (fREF = 16MHz)
fOUT (QA) (MHz) MIN 680 340 170 MAX 1360 680 340 170 85 42.5 NA 2 4 8 16 32 64 M 170-340 340-680 170-340 340-680 170-340 340-680 170-340 340-680 170-340 340-680 170-340 340-680 P 2 4 2 4 2 4 2 4 2 4 2 4 G (MHz) 4 2 2 1 1 0.5 0.5 0.25 0.25 0.125 0.125 0.0625
Table 7. Output NB Divider Setting
NB INPUT 0 1 QB DIVIDER RATIO 1 2 OUTPUT FREQUENCY fQB (MHz) f QB = f QA f QB = f QA / 2 DEFAULT VALUE 0 -- 85 42.5 21.25
For a given reference frequency fREF (fXTAL), the PLL feedback divider M must be configured to match the specified VCO frequency range (1360MHz to 2720MHz) to achieve a valid PLL configuration. For example, with fREF = 16MHz and P = 4, M has a valid value between 340 and 680. f f VCO = REF x M P 1360 f VCO 2720 Invalid PLL configuration leads to VCO frequencies beyond the specified lock range and can result in loss of lock. M is chosen to be between 136 and 725 for the whole reference frequency range, 15MHz to 20MHz. The smallest possible change in the output frequency is the synthesizer granularity G (difference in f OUT when incrementing or decrementing M). G is a function of fREF and dividers P, NA, and NB. The MAX3674 typically provides a resolution of less than 1% for granularity G. See Table 8. f REF G= P x N A,B The purpose of the PLL predivider P is to scale the reference frequency for operations within the PLL. The setting for P affects the generator output frequency granularity and PLL loop bandwidth. For a given output frequency, P = 4 results in a finer (smaller) output frequency granularity, G, and a smaller PLL bandwidth compared to the P = 2 setting.
12
Example of Output Frequency Configuration The following steps provide an example of how to determine the appropriate settings for P, M, NA, and NB given that a 16MHz reference (fREF) is available and the desired output frequency (fOUT) is 500MHz with fine granularity (P = 4). 1) Determine the output divider setting for NA that provides an output frequency range that encompasses the desired output frequency. According to Table 8, the desired frequency of 500MHz falls into the fOUT range of 340MHz-680MHz, requiring NA = 4.
2) Calculate the VCO frequency:
f VCO = f OUT x NA In this case, fOUT = 500MHz, NA = 4, giving fVCO = 500MHz x 4 = 2000MHz.
3) Determine the setting for the feedback divider M:
f M = VCO x P f REF The finest granularity is obtained with P = 4, and in this case corresponds to 1MHz (see Table 8). The value for M is then calculated as M = (2000MHz / 16MHz) x 4 = 500.
______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
4) Configure the MAX3674 with the obtained settings:
P = 1b (/ 4 divider, see Table 4) M[9:0] = 0111110100b (binary number for M = 500) NA[2:0] = 100b (/ 4 divider, see Table 6) NB = 0b (/ 1 divider, fQA = fQB)
5) Apply the settings with the parallel or serial interface. The I2C configuration bytes for this example are PLL_L = 11110100b and PLL_H = 01100010b. See Tables 1 and 2 for the registers maps.
Programming Through Serial I2C Interface While PLOAD = 1 the MAX3674 internal registers are read and write accessible through the 2-wire I2C interface using the SDA (configuration data) and SCL (configuration clock) signals. The MAX3674 acts as a slave device on the I 2 C bus, supporting fast-mode data transfer rates up to 400kbps.
The internal registers include two configuration registers (PLL_L and PLL_H), a command register (CMD), and an ID register (ID). See Tables 1 and 2 for the register maps. Registers PLL_L and PLL_H store a PLL configuration and provide full read/write access through the serial I2C interface. Register CMD is write only and accepts commands (LOAD, GET, INC, DEC) to update registers and for direct PLL frequency changes. The CMD register provides a fast way to increase or decrease the synthesizer frequency and to update the PLL_L and PLL_H registers. LOAD and GET are inverse commands to each other. LOAD copies the data stored in the configuration registers into the PLL divider latches. GET copies the PLL dividers settings into the configuration registers (PLL_L, PLL_H). INC (DEC) directly increments (decrements) the PLL feedback divider M (M := M + 1, M := M - 1) and immediately changes the PLL frequency by the granularity step G (see Table 8 for available G) in a single I2C transfer without using the LOAD command. The INC and DEC commands are useful for frequency margining applications that require multiple and rapid PLL frequency changes. Note that the INC and DEC commands do not update the PLL_L and PLL_H registers. It is, therefore, recommended to use LOAD to set a valid PLL divider setting before using INC or DEC. In addition, the synthesizer does not check the validity of divider settings for proper operation bounded by the VCO range. So, applying the DEC and INC commands can result in invalid VCO frequencies and lead to loss of lock. Programming the synthesizer output frequency through the serial I2C interface requires two steps: writing a valid PLL configuration to the configuration registers and loading the register data into the PLL divider latches with an I2C command. The PLL frequency is affected as a result of the second step. The two-step operations can be performed by a single I2C transaction or by multiple
MAX3674
Programming Through Parallel Interface The parallel interface comprises 15 pins (P, M[9:0], NA[2:0], and NB) for configuring the PLL frequency setting. The parallel interface is enabled with the PLOAD input set to logic-low. While PLOAD remains low, any logical state change on the 15 parallel pins immediately affects the internal divider settings, resulting in a change of the internal VCO frequency and the output frequency. Upon startup, when the device master reset signal is released (rising edge of the MR signal), the device reads its startup configuration through the parallel interface and is independent of the PLOAD state. For startup, it is recommended to provide a valid PLL configuration (satisfying the VCO frequency range constraint). If all the parallel interface pins are left open, a default PLL configuration is loaded (Table 9). While in parallel mode operation (PLOAD = 0), the I2C write access is disabled. Therefore, all data written into the MAX3674 registers through I2C is ignored. However, the MAX3674 is still present on the I2C interface and is read accessible, allowing the host controller to read the internal registers through the I2C interface for monitoring purpose. In parallel mode (PLOAD = 0), I2C register access is limited to read only, implying that CMD register access is invalid. The MAX3674 allows read access to registers PLL_L, PLL_H, and ID through I2C and can verify the divider setting since the current PLL configuration in parallel mode is always stored in PLL_L and PLL_H.
After the low-to-high transition of PLOAD, the configuration pins have no more effect, and the programming interface is now accessible through the serial I2C interface.
Table 9. Parallel Interface Default
PARALLEL INTERFACE DEFAULT VALUE M[9:0] 01 1111 0100 NA[2:0] 010 NB 0 P 1 f OUT, QA (fREF = 16MHz) 250MHz
______________________________________________________________________________________
13
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
independent I2C transactions. Alternatively, small frequency changes can be made in one step using the increment and decrement commands. The following are three examples using the serial I2C interface. Example 1: Set the synthesizer frequency. 1) Write the PLL_L and PLL_H registers with a valid configuration.
Register Read/Write Transfer
Write Mode (R/W = 0) The host controller writes the configuration registers by initiating a write transfer with the MAX3674 slave address (first byte), followed by the address of the configuration register (second byte: 0x00, 0x01, or 0xF0), and the configuration data byte (third byte). This transfer can be followed by writing more registers by sending the configuration register address followed by one data byte. The MAX3674 acknowledges each byte sent by the host controller. The transfer ends by a stop bit sent by the host controller. The number of configuration data bytes and the write sequence are not restricted. Table 10 shows an example of the complete configuration register write transfer. Read Mode (R/W = 1) The host controller reads the configuration registers by initiating a read transfer. The MAX3674 supports read transfer immediately after the first byte without a change in the transfer direction. Immediately after the host controller sends the slave address, the MAX3674 acknowledges and then sends the configuration registers and identification (PLL_L , PLL_H, and ID) back-to-back to the host controller. The CMD register cannot be read. To read the two configuration registers and the current PLL settings, the user can read PLL_L and PLL_H, write the GET command (loads the current configuration into PLL_L and PLL_H), and read PLL_L and PLL_H again. Table 11 shows the complete register read transfer. Note that the PLL_L and PLL_H registers and divider settings may not be equivalent after the following example cases: * Writing the INC command.
2) Write the LOAD command to update the PLL
dividers with the current PLL_L, PLL_H content. Example 2: Read the synthesizer frequency. 1) Write the GET command to update the PLL_L, PLL_H registers with the PLL divider settings.
2) Read the PLL_L, PLL_H registers through I 2 C
protocol. Example 3: Change the synthesizer frequency in small steps. 1) Write the INC or DEC command to change the synthesizer frequency by granularity step G. The ID register is read only, used for the purpose of identification. When a read command is sent to the MAX3674, the content in ID is sent back to the controller together with the data in PLL_L and PLL_H, so a system can use this information accordingly. See Table 11. When changing parallel mode into serial mode, at the rising edge of PLOAD input, the MAX3674 internal register contents and frequency divider configurations are not changed until rewritten by the user through the serial I2C interface. However, when changing serial mode into parallel mode, at the falling edge of PLOAD input, the internal register contents and frequency divider configurations immediately reflect the logic state of the hardwired pins (M[9:0], NA[2:0], NB, and P).
* Writing the DEC command. * Writing the PLL_L, PLL_H registers with a new configuration and not writing the LOAD command.
Table 10. Configuration Register Write Transfer
1 BIT Start -- 7 BITS Slave Address 10110xx 1 BIT R/W 0 1 BIT ACK -- S 8 BITS &PLL_H 0x01 M 1 BIT ACK -- S 8 BITS ConfigByte 1 Data M 1 BIT ACK -- S 8 BITS &PLL_L 0x00 M 1 BIT ACK -- S 8 BITS ConfigByte 2 Data M 1 BIT ACK -- S 1 BIT Stop -- M
M M M M = master, S = slave.
14
______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
Table 11. Configuration Register Read Transfer
1 BIT Start -- M 7 BITS Slave Address 10110xx M 1 BIT R/W 1 M 1 BIT ACK -- S 8 BITS PLL_L Content Data S 1 BIT ACK -- M 8 BITS PLL_H Content Data S 1 BIT ACK -- M 8 BITS ID Content Data S 1 BIT Non-ACK -- M 1 BIT Stop -- M
M = master, S = slave.
Device Startup and Reset
General Device Configuration It is recommended to apply a master reset signal (MR = 0) during or immediately after the system power-up. Upon the release of this master reset signal at the lowto-high transition of the MR, the MAX3674 automatically acquires a startup configuration from the parallel interface pins (M[9:0], NA[2:0], NB, and P) independent of the PLOAD input status. If all parallel interface pins are left open, the MAX3674 loads its internal default values for each divider setting as the startup condition.
The MAX3674 acquires frequency lock within the specified lock time, tLOCK, and is indicated by an assertion of the LOCK signal, which completes the startup procedure. It is recommended to disable the outputs (CLK_STOPx = 0) until PLL lock is achieved to suppress output frequency transitions. The output frequency can be reconfigured at any time through either the parallel or the serial interface. Upon applying a master reset (MR = 0), the I2C logic is also reset and restored to a valid state, and all the register contents are set to the default values. Read and write access is not permitted while master reset is asserted (MR = 0).
the outputs by setting CLK_STOPx = 1. PLL lock or relock (after any configuration change through M or P) is indicated by assertion of LOCK output. See Figure 2 for the timing diagram.
VCC MR LOCK M, NA, NB, P PLOAD CLK_STOPx QA, QB OUTPUTS DISABLED LOW PLL LOCK TIME STABLE AND VALID 1 OR 0, DON'T CARE SELECTS I2C
Figure 2. Startup Using I2C Interface
LOCK Detect
The LOCK detect circuitry indicates the frequency lock status of the PLL by setting and resetting the pin LOCK and register bit LOCK simultaneously. Attempts to write the LOCK bit through the serial I 2 C interface are ignored. The LOCK status is asserted after the PLL acquires frequency lock during any configuration change to the MAX3674, such as the startup, the update of the PLL output frequency, etc. The LOCK status is immediately deasserted when the PLL loses lock; for instance, when the PLL feedback divider M or predivider P is changed, or master reset is asserted. The PLL may not lose lock as a result of slow or small reference frequency changes. LOCK assertion and deassertion is indicated by the LOCK signal after a delay to prevent transient PLL status change during frequency transitions. A valid reference clock is required to update the LOCK register. An interrupted reference clock makes the LOCK output indeterminate. In bypass mode (BYPASS = 0), LOCK becomes a production test output.
15
Starting Up Using the Parallel Interface In this mode, the serial interface pins (SDA, SCL, and ADR[1:0]) can be left open and PLOAD is set to logiclow. After release of MR and at any other time, the synthesizer configuration is directly set according to the inputs through the M[9:0], NA[2:0], NB, and P pins. Starting Up Using the Serial (I2C) Interface In this mode, set PLOAD = 1, CLK_STOPx = 0 (suppressing output frequency transitions). Upon the rising edge of MR, the MAX3674 dividers are configured by the default setting of the parallel interface pins independent of the PLOAD input status. This initial PLL configuration can be reprogrammed to the final setting at any time through the serial interface. After the PLL achieves lock at the desired VCO frequency, enable
______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
ENABLE CLK_STOPx DISABLE ENABLE
Qx
tDIS
tEN
Figure 3. Clock Stop Timing for NB = 1 (fQA = fQB)
CLK_STOPA, CLK_STOPB
ENABLE DISABLE
ENABLE
QA
QB
Figure 4. Clock Stop Timing for NB = 2 (fQA = 2 x fQB)
Output Clock Stop
Assertion of CLK_STOPx stops the respective output clock in a logic-low state (Qx = low, Qx = high). The CLK_STOPx control is internally synchronized to the output clock signal, and enabling and disabling outputs does not produce runt pulses. See Figure 3. The clockstop controls of the QA and QB outputs are independent of each other. If the QB runs at half the QA output frequency and both outputs are enabled at the same time, the first clock pulse of QA may not appear at the same time as the first QB output (Figure 4). Coincident rising edges of QA and QB stay synchronous after the assertion and deassertion of the CLK_STOPx controls. Asserting MR asynchronously forces the output buffer to a logic-low state, with the risk of producing an output runt pulse.
power-supply pin, VCC_PLL, for the PLL circuitry. The purpose of this design technique is to ensure clean input power supply to the sensitive PLL circuitry and to improve the overall immunity to power-supply noise. Figure 5 illustrates the recommended power-supply filter network.
RF = 10 VCC = 3.3V CF = 22F 10nF VCC_PLL
MAX3674
VCC 33nF-100nF
VCC_PLL Filter The MAX3674 is a mixed-analog/digital IC. The PLL contains analog circuitry susceptible to random noise. To take full advantage of on-board filtering and noise attenuation in addition to excellent on-chip power-supply noise rejection, the MAX3674 provides a separate
7
Figure 5. PLL Power-Supply Filtering Network
16
______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
The minimum values for RF and CF should be chosen to achieve greater than 40dB attenuation for noise whose spectral content is above 100kHz, as is the case for the recommended filter. Another important aspect to the filter design is the DC voltage drop between the VCC supply and the VCC_PLL pin. The DC Electrical Characteristics table specifies a maximum 10mA PLL supply current (the current sourced into the VCC_PLL pin) with a minimum 3.035V supply voltage at the VCC_PLL pin. The minimum voltage at the VCC_PLL pin is met over the full VCC range (+3.3V 5%) with RF 10. The parallel capacitor combination shown in Figure 5 ensures that a low-impedance path to ground exists for a wide band of frequencies, including frequencies well above the PLL bandwidth. For optimal performance, filter capacitors should be placed as close to the supply pins as possible.
MAX3674
VCC
Qx Qx
ESD STRUCTURES
Jitter Analysis When NB = 2 (fQA = 2 x fQB) The high-frequency outputs, QA and QB, are synchronized on the rising edges. Using the postdivider NB, the outputs can be configured such that fQA = fQB with NB = 1, or fQA = 2 x fQB with NB = 2. See Figure 4 for a timing diagram. In the case where NB = 1, both outputs have corresponding rising and falling edges, and generate cycle-to-cycle and period jitter with normal Gaussian distributions. In the case where NB = 2, rising edges of the two outputs correspond every other QA cycle, causing the cycle-to-cycle and period jitter distributions to be bimodal on the QA output. The QB jitter distribution remains normal Gaussian in both cases (NB = 1 or 2). See the peak-to-peak jitter graphs in the Typical Operating Characteristics for comparisons of the two cases. Interfacing with LVPECL Outputs
Figure 6 shows the equivalent LVPECL output circuit. These outputs are designed to drive a pair of 50 transmission lines DC terminated 50 to VTT = VCC 2V. If a separate termination voltage (VTT) is not available, other terminations methods can be used such as shown in Figures 7 and 8. Unused outputs should be disabled and left open. For more information on LVPECL terminations and how to interface with other logic families, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML.
Figure 6. Equivalent PECL Output Circuit
VCC
130 Z = 50 Qx Z = 50
130
82
82
MAX3674
Figure 7. Thevenin Equivalent Termination
0.22F Z = 50 Qx 0.22F Z = 50 100
143
143
MAX3674
Figure 8. AC-Coupled Termination
______________________________________________________________________________________
17
High-Performance, Dual-Output, Network Clock Synthesizer MAX3674
Crystal Oscillator
The MAX3674 features an integrated crystal oscillator to minimize system implementation cost. The integrated oscillator is a Pierce-type that uses the crystal in its parallel resonance mode. It is recommended to use a 15MHz to 20 MHz crystal with a load specification of CL = 10pF. See Table 12 for the recommended crystal specifications. Crystals with a load specification of CL = 20pF can be used at the expense of a resulting slightly higher frequency than specified for the crystal. Externally connected capacitors on both the XTAL1 and XTAL2 pins are not required but can be used to finetune the crystal frequency as desired. The crystal, trace, and optional capacitors should be placed on the board as close as possible to the MAX3674 XTAL1 and XTAL2 pins to reduce crosstalk of active signals into the oscillator. Short and wide traces further reduce parasitic inductance and resistance.
Board Layout
Circuit-board trace layout is very important to maintain the signal integrity of high-frequency differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, and not using sharp corners or vias. Ensure the two traces are parallel and close to each other to increase common-mode noise immunity and reduce EMI. Matching the electrical length of the differential traces further reduces signal skew.
Table 12. Recommended Crystal Specifications
PARAMETER Crystal Cut Resonance Mode Crystal Frequency Shunt Capacitance, C0 Load Capacitance, CL Equivalent Series Resistance (ESR), RS Maximum Crystal Drive Level VALUE Fundamental AT cut Parallel 15MHz to 20MHz 5pF to 7pF 10pF 20 to 60 200W
18
______________________________________________________________________________________
High-Performance, Dual-Output, Network Clock Synthesizer
Pin Configuration
TEST_EN LOCK
MAX3674
GND
TOP VIEW
36
35
34
33
32
31
30
29
28
27
GND
VCC
VCC
VCC
NB
QA
QA
QB
QB
26
GND NA2 NA1 NA0 PLOAD VCC MR SDA SCL ADR1 ADR0 P
25
37 38 39 40 41 42 43 44 45 46 47 48
24 23 22 21 20 19
M9 M8 M7 M6 M5 GND M4 M3 M2 M1 M0 VCC
MAX3674
18 17 16 15 14
+
10 11 12 1 2 3 4 5 6 7 8 9
13
CLK_STOPA
CLK_STOPB
REF_SEL
REF_CLK
XTAL1
BYPASS
VCC_PLL
LQFP
XTAL2
GND
GND
VCC
VCC
Chip Information
TRANSISTOR COUNT: 96,136 PROCESS: CMOS
PACKAGE TYPE 48 LQFP
Package Information
(For the latest package outline information, go to www.maxim-ic.com/packages.) DOCUMENT NO. 21-0054
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX3674ECM

	To Download MAX3674ECM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .